六进制计数器行为描述与RTL描述

library ieee;
use ieee.std_logic_1164.all;
entity ImageDemo1 is
port(
	clk:in std_logic;
	rs:in std_logic;
	count_out:out std_logic_vector(2 downto 0));
end ImageDemo1;
architecture behav of ImageDemo1 is
	signal next_count:std_logic_vector(2 downto 0);
begin
	count_proc:process(rs,clk)
  begin
	if rs='0' then
		next_count<="000";
	elsif(clk'event and clk='1') then
		case next_count is
		  when "000"=>next_count<="001";
		  when "001"=>next_count<="011";
		  when "011"=>next_count<="111";
		  when "111"=>next_count<="110";
		  when "110"=>next_count<="100";
		  when "100"=>next_count<="000";
		  when others=>next_count<="XXX";
		end case;
	end if;
	count_out<=next_count after 10ns;
	end process;
end behav;

library ieee;
use ieee.std_logic_1164.all;
entity ImageDemo1 is
port(clk,rs:in std_logic;
	q0,q1,q2:out std_logic);
end ImageDemo1;
architecture rtl of ImageDemo1 is
component dff
	port(d,rs,clk:in std_logic；
		q:out std_logic);
end component;
component djk
	port(j,k,rs,clk:in std_logic;
		q:out std_logic);
end component;
component and2
	port(a,b:in std_logic;
		c:out td_logic);
end component;
component nor2
	port(a,b:in std_logic;
		c:out std_logic);
end component;
signal jin,kin,q0_out,q1_out,q2_out:std_logic;
begin
	u1:nor2
		port map(q1_out,q0_out,jin);
	u2:and2
		port map(q2_out,q0_out,kin);
	u3:djk
		port map(jin,kin,rs,clk,q0_out);
	u4:dff
		port map(q0_out,rs,clk,q1_out);
	u5:dff
		port map(q1_out,rs,clk,q2_out);
	q0<=q0_out;
	q1<=q1_out;
	q2<=q2_out;
end rtl;